1. Field of the Invention
The present invention relates generally to semiconductor devices. More particularly, this invention relates to a dual vertical channel, dual-gate fin field-effect-transistor (FinFET) with buried bit line scheme, and fabrication method thereof.
2. Description of the Prior Art
A vertical fin field-effect-transistor (FinFET) with embedded or buried bit line scheme has become the mainsteam for next-generation 4F2 (F stands for minimum lithographic feature width) cell because of simplified middle-of-line (MOL) process. However, front-end-of-line (FEOL) process becomes more complicated accordingly. For example, shallow trench isolation (STI) with half feature size and an aspect ratio of STI larger than 20 are required for 30 nm generation. Gap fill with oxide film thus becomes an obstacle to dynamic random access memory (DRAM) shrinkage.
Vertical surrounding gate transistors (SGT) with embedded bit lines have been proposed with enlarging isolation rule to greatly reduce difficulty during the STI phase. However, threshold voltage (Vth) stability for the memory cell array becomes much worse because of complicated fabricating process, including, for example, tedious embedded bit line formation steps, recess for spin-on-dielectric (SOD) formation steps, metal and n+ type poly defined transistor gate length. Reducing Vth variation with longer channel length is also unfeasible under vertical dimension constraint.
Further, it has been known that the DRAM array incorporated with the aforesaid vertical FinFET structure with buried bit line scheme face different challenges. For example, parasitic bipolar transistor induced by floating body effect, which causes array Vth instability during cell operation. It has been found that excess majority carriers generated by impact ionization at bit line junction and accumulated in neutral body can reduce transistor threshold voltage. With increasing Ioff, the retention becomes worse.
In light of the above, there is a strong need in this industry to provide a novel FinFET structure and the fabrication process therefore to avoid the aforesaid problems.